1. Field of the Invention
The present invention relates to a semiconductor device having a shallow trench isolation (hereinafter, referred to as STI) structure and a method for manufacturing the same.
2. Description of the Related Art
Much progress has been made in increasing speed and integration of semiconductor devices. Along with this progress, higher-density patterns and reduction in size has become increasingly important. Wide isolation regions in semiconductor devices have also made higher-density patterns and reduced sizes a requirement.
Local oxidation of silicon (LOCOS) layers have been mainly used as conventional isolation layers of semiconductor devices. However, bird""s beak configurations are created at the edges of the isolation layer by the LOCOS method and thus the area of active regions is reduced and current leakage occurs.
Recently, shallow trench isolation (STI) layers having narrow widths and excellent isolation characteristics have been proposed and a semiconductor device having such STI structure will be described with reference to FIG. 1.
Referring to FIG. 1, a blocking pattern (not shown) is formed on a semiconductor substrate 10 to expose an isolation region. The semiconductor substrate 10 can be defined as a cell area, a core area and a peripheral area. In addition, the blocking pattern may be a stack of an oxide layer and a silicon nitride layer. The exposed semiconductor substrate 10 is etched to a predetermined depth using the blocking pattern as a mask, thereby forming trenches t1 and t2 therein. The trench t1 is formed in the cell area and the trench t2 defines a P-channel field effect transistor (P-FET) area in the core or peripheral areas. A dry etching process is performed for forming the trenches t1 and t2 using a plasma.
The dry etching process for forming the trenches t1 and t2, however, may cause silicon lattice defects and damage inner surfaces of the trenches t1 and t2. Conventionally, to reduce such silicon lattice defects and damage, a sidewall oxide layer 12 is formed by thermally oxidizing the inner surfaces of the trenches t1 and t2. Also, the formation of a sidewall oxide layer 12 smoothens sharp corners of the trenches t1 and t2.
Afterwards, a silicon nitride liner 14 is formed on the surface of the sidewall oxide layer 12. As is well known, the silicon nitride liner 14 prevents the generation of stress caused by the coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate 10 formed of silicon and a silicon oxide layer with which the trenches t1 and t2 will be filled.
A dielectric material, for example, a high-density-plasma (HDP) dielectric layer is deposited over the resultant semiconductor substrate 10 to completely fill the trenches t1 and t2. Next, chemical mechanical polishing (hereinafter, referred to as xe2x80x9cCMPxe2x80x9d) is performed on the HDP dielectric layer and the blocking pattern to expose the surface of the semiconductor substrate 10. This completes the formation of an STI layer 16.
However, semiconductor devices having the conventional STI structure causes the following problems. With reference to FIGS. 2A and 2B, since hot carriers of a highly integrated semiconductor MOS transistor generally have high energy, they bounce to a thin gate oxide layer 22 or easily penetrate through the sidewall oxide layer 12 into the STI layer 16. The hot carriers penetrating into the STI layer 16 are mainly negative charges, namely, electrons 30, which are easily trapped in the silicon nitride liner 14 in the STI layer 16 and on the interface between the silicon nitride liner 14 and the sidewall oxide layer 12. At this time, the electrons 30 are closely trapped since the sidewall oxide layer 12 is remarkably thin as described above. In the case where the electrons 30 are dense with the edge of the STI layer 16, positive charges of the semiconductor substrate 10 on which MOS transistors are formed, namely, holes 32 are induced to the circumference of the STI layer 16. At this time, since the electrons 30 are closely trapped in the silicon nitride liner 14 and on the interface between the silicon nitride liner 14 and the sidewall oxide layer 12, the holes 32 in the semiconductor substrate 10 are densely gathered together.
As shown in FIG. 2A since in an N-channel field effect transistor (N-FET) major carriers are the electrons 30, a path is not formed between n-type junction areas 26a and 26b in which the electrons 30 function as major carriers even though the holes 32 are dense with the circumference of the STI layer 16.
As is well known, since, in a P-FET, major carriers are the holes 32, as shown in FIG. 2B, the holes 32, which are densely populated at the circumference of the STI layer 16, form a current path I connecting p-type junction areas 28a and 28b isolated by the STI layer 16. Consequently, due to the current path I, although p-type junction areas 28a and 28b are isolated by the STI layer 16, leakage current, such as abnormally increased standby current after burn-in, occurs between adjacent P-FETs, thereby deteriorating the characteristics of the P-FETS. Here, reference numeral 24 denotes a gate electrode of a MOSFET.
Furthermore, if a P-FET (not shown) is on the interface between the STI layer 16 and an active region, a channel area of the P-FET abuts the silicon nitride liner 14, in which the electrons are trapped, by the thin sidewall oxide layer 12. Consequently, the electrons trapped in the silicon nitride liner 14 easily induce holes to the channel area of the P-FET in the interface. Also, the holes induced in turning on the P-FET are not easily removed and remain when turning off the P-FET. Thus, the length of the channel of the P-FET on the interface is gradually reduced, thereby decreasing threshold voltage and breakdown voltage. Consequently, the characteristics of the P-FET are undesirably altered.
To solve the above problems, the present invention provides a semiconductor device having a shallow trench isolation (STI) structure, which can reduce leakage current of the semiconductor device around an STI layer.
The present invention also provides a method of manufacturing of the semiconductor device having the STI structure.
According to a first embodiment of the present invention, the semiconductor device having an STI structure includes a semiconductor substrate having a plurality of trenches providing isolation in a cell area in which memory devices are formed, and in non-cell areas, e.g., core or peripheral areas in which P-FETs and other circuit devices are formed. A first sidewall oxide layer is formed on the inner surfaces of the plurality of trenches. A second sidewall oxide layer is formed on first sidewall oxide layer in one or more of the plurality of trenches in the non-cell areas. A first relief liner is formed on the first sidewall oxide layer in one or more of the plurality of trenches in the cell area. A second relief liner is formed on the first relief liner and also on the second sidewall oxide layer. The plurality of trenches are filled with a dielectric material.
According to a second embodiment of the present invention, the semiconductor device having an STI structure includes a semiconductor substrate having a plurality of trenches for isolating a cell area in which memory devices are formed and core or peripheral areas in which a P-FET and other circuit devices are formed and between devices formed in respective areas. A first sidewall oxide layer is formed on the inner surfaces of the plurality of trenches. A second sidewall oxide layer is formed on the first sidewall oxide layer in one or more of the plurality of trenches isolating between P-FETs in the core or peripheral areas. A first relief liner is formed on the first sidewall oxide layer in one or more of the plurality of trenches isolating between memory devices in the cell area and between the other circuit devices in the core or peripheral areas. A second relief liner is formed on the first relief liner, and also on the second sidewall oxide layer. The plurality of trenches are filled with a dielectric material. The first sidewall oxide layer has a thickness of about 20xcx9c50 xc3x85. The second sidewall oxide layer has a thickness of about 50xcx9c100 xc3x85. The first and second relief liners are formed of silicon nitride or silicon oxynitride. The dielectric material is a HDP layer or a TEOS layer.
According to another aspect of the present invention, a method of manufacturing a semiconductor device having an STI structure is as follows. There is provided a semiconductor substrate including a cell area in which memory devices are formed and non-cell areas, e.g., core or peripheral areas in which a P-FET and other circuit devices are formed. A blocking pattern is formed on the semiconductor substrate to expose a predetermined area for defining the cell, core or peripheral areas of the semiconductor substrate and for isolating between devices in respective areas. A plurality of trenches are formed by etching a pre-isolation area of the exposed semiconductor substrate to a predetermined depth using the blocking pattern as a mask. A first sidewall oxide layer is formed on the inner surfaces of the plurality of trenches. A first relief liner is formed over the first sidewall oxide layer. A region of the first sidewall oxide layer is exposed by removing a portion of the first relief liner formed in a selected area including a trench providing isolation between P-FETs among the plurality of trenches. A second sidewall oxide layer is selectively formed on the exposed surface of the first sidewall oxide layer. A second relief liner is formed on the first relief liner and also on the second sidewall oxide layer. A dielectric material is deposited to fill the plurality of trenches. An STI layer is formed by planarizing the dielectric layer, the relief liners, and the blocking pattern.
The first and second sidewall oxide layers are formed by a thermal oxidation method. The first and second relief liners are formed of silicon nitride or silicon oxynitride. The first relief liner in the selected area is removed by an isotropic etching method.
The selected area may include a trench isolating between P-FETs in the core or peripheral areas.
Forming the blocking pattern may include forming a pad oxide layer on the semiconductor substrate, forming a silicon nitride layer on the pad oxide layer, and patterning the silicon nitride layer and the pad oxide layer to expose the predetermined area.
According to the present invention, the STI layer, which provides isolation between the core or peripheral areas or between P-FETs in the core or peripheral areas, has a relatively thick sidewall oxide layer. The STI layer formed in the cell area has a relatively thick relief liner.
Because the sidewall oxide layer of the STI layer isolating between P-FETs in the core or peripheral areas is relatively thick, the electrons trapped in the relief liner and on the interface between the liner and the sidewall oxide layer are widely distributed and holes induced from the electrons are also widely distributed on the outer face. Consequently, a current path is not formed. As a result, a leakage current path between adjacent P-FETs is not generated. Also, the threshold voltage and breakdown voltage characteristics of the P-FET on the interface are not deteriorated.
In addition, as the relief liner of the STI layer formed in the cell area is relatively thick, the thick relief liner prevents the penetration of the defects generated in the cell area into the STI layer. Consequently, an STI layer having excellent dielectric characteristics can be provided.